This Technical Reference Manual is intended primarily to assist writers of software for the Amstrad PPC, although in conjunction with the PPC Service Manual it will be of interest to designers of add-on hardware.

It is assumed that the reader has a working knowledge of the Industry Standard architecture comprising of an 8086 (or 8088) with DMA, PIT, RTC and Interrupt Controller support chips; plus Colour Graphics Adapter (or Monochrome Graphics Adapter) with Floppy Disk, Serial and Parallel Adapters.

The information contained herein is largely unique to this document, with the exception of parts of the appendices which expand on the information contained in the PPC User Instructions and the Microsoft MSDOS Reference Manual.

Whilst the PPC implements a superset of the Industry Standard, this manual makes no attempt to identify those areas of the PPC specification which exceed the Industry Standard. Users should, therefore, exercise caution when writing software for a range of manufacturers' PCs and only use the "Lowest Common Denominator" facilities if simple portability is required.

Please note, that communications regulations do not allow the release of technical information relating to the circuitry or construction of the PC2000 modem.

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© Copyright 1988 Amstrad Consumer Electronics Plc

Neither the whole nor any part of the information contained herein, nor the product described in this manual may be adapted or reproduced in any form except with the prior approval of Amstrad Consumer Electronics Plc ('Amstrad').

All information of a technical nature and particulars of the product are given by Amstrad in good faith. However, it is acknowledged that there may be errors or omissions in this manual.

All correspondence should be addressed to:

All maintenance and service on the product must be carried out by Amstrad authorised dealers. Amstrad cannot accept any liability whatsoever for any loss or damage caused by service or maintenance by unauthorised personnel. This manual is intended to assist the reader in the use of the product, and therefore Amstrad shall not be liable for any damage or loss whatsoever arising from the use of any information or particulars in, or any error or omission in, this manual or any incorrect use of the product.

Written by Bill Weidenauer and edited by Susan Vass, Amstrad plc.

Published by Amstrad.

First Published 1987.

MS-DOS(R) is a registered trademark of Microsoft(R) Corporation

Amstrad is a registered trademark of Amstrad plc.

Unauthorised use of the trademark or the word Amstrad is strictly forbidden.

Table of Contents:

Section 1 - Hardware

1.0 Introduction				1
	1.1 Central Processing Unit (CPU)			1
	1.2 Memory Layout			2
	1.3 Main Board I/O Channels			3
	1.4 Expansion Bus I/O Channels			5
	1.5 Direct Memory Access (DMA)			5
		1.5.1 DMA Page Registers		6
		1.5.2 DMA Initialization		7
	1.6 System Interrupts			7
		1.6.1 Interrupt Levels		8
		1.6.2 Interrupt Controller Initialization		8
		1.6.3 NMI Mask Control		9
	1.7 Programmable Interval Timers			9
		1.7.1 Timer Configuration		10
		1.7.2 Counter 1 initialization		10
	1.8 System Status and Control			10
		1.8.1 Port B - System Control		11
		1.8.2 Port A - Status-1 Input / Keyboard Code		12
		1.8.3 Port C - Status-2 Input		13
		1.8.4 Write System Status-1		14
		1.8.5 Write System Status-2		14
		1.8.6 System Reset		14
	1.9 Real Time Clock			15
	1.10 Parallel Printer Port			15
		1.10.1 Printer Data Latch		16
		1.10.2 Printer Control Latch		16
		1.10.3 Printer Status Channel		17
	1.11 The Internal display Adapter			18
		1.11.1 Colour Alpha Display		19
		1.11.2 Colour Graphics Display		21
			1.11.2.1 Low Resolution Graphics	21
			1.11.2.2 Medium Resolution Graphics	22
			1.11.2.3 High Resolution (640 X 200) Graphics Mode	23
		1.11.3 Monochrome Display		23
		1.11.4 BIOS Modes		24
		1.11.5 Colour Mode Registers.		25
			1.11.5.1 CGA Mode Control Register	25
			1.11.5.2 Colour Select Register	26
			1.11.5.3 CGA Status Register	27
			1.11.5.4 CGA Mode CRTC initialization.	27
			1.11.5.5 Set and Clear Light Pen Latch	29
			1.11.5.6 Operation Control/Status Register	29
			1.11.5.7 CRTC Index Readback	30
			1.11.5.8 CRTC Data Readback	30
		1.11.6 Monochrome Mode Registers.		31
			1.11.6.1 MDAMode Control Register	31
			1.11.6.2 MDAStatus Register	32
			1.11.6.3 Monochrome CRTC initialization.	32
	1.12 Floppy Disk Controller			34
		1.12.1 FDC Hardware Conditions		34
	1.13 RS232C Asynchronous Serial Port			35
		1.13.1 Serial Channnel Interface		35
		1.13.2 Serial Channnel Pin Arrangement		36
	1.14 Parallel Printer Interface			36
	1.15 Keyboard Interface			38
		1.15.1 Serial Clock and Serial Data		38
		1.15.2 Keyboard to Main Board Interface		38
		1.15.3 Main Board to Keyboard Interface		38
		1.15.4 Keycodes		39
	1.16 Modem Interface			39
		1.16.1 Modem Connector		39
	1.17 Light Pen Connector			40
	1.18 Expansion Interface Connectors			41
	1.19 Video Connector			44
	1.20 Power Connectors			45
		1.20.1 The Adapter Power Connector		45
		1.20.2 The Display Power Connector		45
	1.21 PPC Switch Settings			46
2.0 Firmware				47
	2.1 Power-Up Initialization and Self Test			47
	2.2 Power-Up Self Tests			52
		2.2.1 Test Procedure.		52
		2.2.2 Test Methods.		53
		2.2.3 ROS Checksum Test.		53
		2.2.4 Direct Memory Access Controller test.		54
		2.2.5 Programmable Interval Timer test.		54
		2.2.6 Programmable Peripheral Interface test.		54
		2.2.7 Real Time Clock test.		54
		2.2.8 Asynchronous Communications Element test.		54
		2.2.9 Printer Parallel Port test.		54
		2.2.10 System RAM test.		54
		2.2.11 Programmable Interrupt Controller test.		55
		2.2.12 Disk test.		55
		2.2.13 Keyboard Interface test.		55
	2.3 ROM Firmware Interrupts.			55
		2.3.1 Interrupt 2: Parity Error (NMI).		55
		2.3.2 Interrupt 5: Print Screen.		56
		2.3.3 Interrupt 8: System Clock Interrupt		56.
		2.3.4 Interrupt 9: Keyboard Interrupt.		57
			2.3.4.1 Special Key Actions	61
		2.3.5 Interrupt 14: Floppy Disk Controller.		62
		2.3.6 Interrupt 16: Video I/O.		62
		2.3.7 Interrupt 17: System Configuration.		71
		2.3.8 Interrupt 18: Memory Size.		72
		2.3.9 Interrupt 19: Disk I/O.		72
			2.3.9.1 Hard Disk Call Parameters and Registers	77
		2.3.10 Interrupt 20: Serial I/O.		79
		2.3.11 Interrupt 22: Keyboard I/O.		83
		2.3.12 Interrupt 23: Printer I/O.		87
		2.3.13 Interrupt 24: System Restart.		88
		2.3.14 Interrupt 24: Disk Bootstrap.		89
		2.3.15 Interrupt 26: System Clock & Real Time Clock.		89
		2.3.16 Interrupt 27: Keyboard Break Interrupt.		93
		2.3.17 Interrupt 28: External Ticker Interrupt.		93
		2.3.18 Interrupt 29: Video Parameter Table.		93
		2.3.19 Interrupt 30: Disk Parameter Table.		95
		2.3.20 Interrupt 31: Video Matrix Table.		95
	2.4 System RAM Variables.			96
	2.5 Non Volatile RAM.			103
	2.6 ROS Messages.			104
		2.6.1 Non-Fatal ROS Messages.		104
		2.6.2 Fatal ROS Messages.		105
3.0 Reference Information.				106
	3.1 Language Links.			106
	3.2 Processor Memory Usage.			106
	3.3 Asynchronous Communications Element (8250) Registers.			107
	3.4 High Performance Programmable DMA Controller (8237A-4) Registers			110
	3.5 Programmable Interrupt Controller (8259A-2) Command Words.			112
	3.6 Programmable Interval Timer (8253) Registers.			115
	3.7 Real Time Clock (HD146818) Registers			116
		3.7.1 Time, Calendar and Alarm Locations		117
		3.7.2 RTC Register Locations		119
	3.8 Floppy Disk Controller (uPD765A).			121
	Appendix 1: MS-DOS System Configuration			137
	Appendix 2: Country Dependent Information for MS-DOS 3			144
	Appendix 3: RS232C Connections			145
	Appendix 4: Printer Lead (PL-2) Wiring Specification			153
	Appendix 5: PPC Power Usage			155
	Appendix 6: ROM Character Set			156
	Appendix 7: Keyboard Keycodes			158
	Appendix 8: Keyboard Layouts			159
	Appendix 9: The LINKER Program			164
	Appendix 10: COMMAND.COM			179
	Appendix 11: The DEBUG Utility Program (DEBUG)			180
	Appendix 12: The EXE2BIN Utility Program			202
	Appendix 13: The EXIT Command			204
	Appendix 14: The RECOVER Utility Program			205
	Appendix 15: The SHARE Utility Program			206
	Appendix 16: The FDISK Utility Program			207
	Appendix 17: The BACKUP Command			218
	Appendix 18: The RESTORE Command			221

 

 

 

1.0 Introduction

This manual provides a comprehensive description of the Amstrad PPC hardware and firmware. General information about the PPC and the delivered operating system software is contained in the Amstrad PPC User Instructions. This manual is intended to satisfy the needs of advanced developers who must have access to the various resources available within the PPC640 and PPC512.

Note that all address constants in this document are hexadecimal. In addition hexadecimal quantities are noted with small letter 'h' terminator to denote that they are in hexadecimal form. Address quantities are not usually annotated this way since they are clearly hexadecimal. Values are presented in hexadecimal form when they are logically bit oriented quantities rather than of purely numerical significance.

1.1 Central Processing Unit (CPU)

The CPU is a low power 8086-2 microprocessor with 1 Megabyte memory addressing capability (See Figure 1.1), running at a clock frequency of 8MHz. The CPU is connected to an on-board 16-bit system memory bus requiring four 125nS timing cycles (T-States) per access resulting in a 500nS memory cycle for 16-bit memory. The CPU is also connected on an on-board 8 bit I/O and memory peripheral bus with a 4 MHz clock, which in turn connects to an external expansion bus. Operations on the 8-bit bus automatically incur 125nS wait states as follows:

Operation	Wait States	Bus Cycle
8-bit (Memory)	4	1.0 μS
16 to 8-bit convert (Memory)	12	2.0 μS
8-bit (I/O)	6	1.25 μS
16 to 8-bit convert (I/O)	16	2.5 μS

The CPU is configured to run in maximum mode and the instruction set may be optionally extended by the addition of an 8087-2 Numeric Data Coprocessor. The 8087 BUSY output is connected directly to the 8086 NOT TEST input.

1.2 Memory Layout

The main board memory consists of 640K bytes of system RAM with parity checking and 16K bytes of system ROM without parity checking.

The 640K byte user RAM starts at CPU memory address 00000 and extends to 9FFFF. Note that the PPC512 has 512K bytes installed memory ending at address 7FFFFh and the address space from 80000h to 9FFFFh may be extended in external 32K byte blocks (up to the 640K maximum).

The 128K byte address space from A0000 to BFFFF is reserved for video regeneration buffers, and is not used by CPU programs. The PPC Internal Display Adapter (IDA) uses the 64K byte address range from B0000 to BFFFF. The segmentation of this memory range is dependent on the display mode (See section 1.11). External display adapters also use this memory address range for their display buffers.

The 192K byte address space from C0000 to EFFFF is reserved for external expansion ROM address space. Hard Disk controllers use the range from C8000 to C9FFF. Additional hard disk controllers may also use the area from CA000 to CD000. The PPC test board uses the ROM area from E0000 to E7FFF.

The 16K byte system ROM is at FC000 to FFFFF and contains the Resident Operating System (ROS) firmware. The 48K byte address range from F0000 to FBFFF is reserved for ROM space expansion. The 16K byte ROS area address bits are partially decoded such that the ROS ROM repeats four times in the F0000 to FFFFF address range.

MEMORY LAYOUT

00000			ON-BOARD DYNAMIC RAM	640K Byte System Memory
		9FFFF
		A0000	128K BYTES VIDEO DISPLAY BUFFERS
		BFFFF
1M BYTE ADDR RANGE		C0000	192K BYTES EXPANSION ROMS
		EFFFF
		F0000	48K BYTES ROS ROM BLOCK REPEATS	64K Byte System ROM area
		FBFFF
		FC000	16K BYTES (ROS) RESIDENT OPERATING SYSTEM ROM
FFFFF

1.3 Main Board I/O Channels

The interfaces on the main board occupy the 8086 I/O addresses as follows:

ADDRESS(hex)	OUTPUT USE	INPUT USE
000 - 00F	8237 DMA Controller	8237 DMA Controller
010 - 01F	Do Not Use	Do Not Use
020 - 021	8259 Interrupt control	8259 Interrupt control
022 - 03F	Do Not Use	Do Not Use
040 - 042	8253 PIT Load Count (0-2)	8253 PIT Read Count (0-2)
043	8253 PIT Load Mode	Undefined
044 - 05F	Do Not Use	Do Not Use
060	No Effect	Port A - Keyboard Code or System Status 1
061	Port B - System Control	Port B - (Readback)
062	No Effect	Port C - System Status-2
063	No Effect	Do Not Use
064	Write System Status-1	Do Not Use
065	Write System Status-2	Do Not Use
066	System Reset	Do Not Use
067 - 06F	Do Not Use	Do Not Use
070	146818 RTC Address	Do Not Use
071	146818 RTC Data	146818 RTC Data
072 - 077	Do Not Use	Do Not Use
078	Reserved	Reserved
079	Do Not Use	Do Not Use
07A	Reserved	Reserved
07B - 07F	Do Not Use	Do Not Use
080	Do Not Use	Do Not Use
081	DMA Page Register Ch 2	Do Not Use
082	DMA Page Register Ch 3	Do Not Use
083	DMA Page Register Ch 0,1	Do Not Use
084 - 09F	Do Not Use	Do Not Use
0A0	NMI Mask Control	Do Not Use
0A1 - 0BF	Do Not Use	Do Not Use
0C0 - 0FF	Reserved	Reserved
2F8 - 2FF	Modem UART Tx Data/Control	Modem UART Rx Data/Control
378	Printer Data Latch	Printer Data Latch
379	Do Not Use	Printer Status
37A	Printer Control Latch	Printer Control Latch
37B - 37F	Do Not Use	Do Not Use
3B0 - 3B7	Mono Mode CRTC Registers	Mono Mode CRTC Registers
3B8 - 3BF	Mono Mode Control Registers	Mono Mode CRTC Registers
3D0 - 3D7	Colour Mode CRTC Registers	Colour Mode CRTC Registers
3D8 - 3DF	Colour Mode Control Registers	Colour Mode Control Registers
3F0 - 3F1	Do Not Use	Do Not Use
3F2	Drive Selection	Do Not Use
3F3	Do Not Use	Do Not Use
3F4	Do Not Use	765 FDC Status
3F5	765 FDC Data	765 FDC Data
3F6 - 3F7	Do Not Use	Do Not Use
3F8 - 3FF	COM1 8250 UART Tx Data/Control	COM1 8250 UART Rx Data/Control

1.4 Expansion Bus I/O Channels

The 8086 CPU I/O addresses on the expansion bus are as follows:

ADDRESS(hex)	USE
200 - 20F	External Game Control Interface
210 - 217	External Bus Expansion Unit
220 - 24F	Reserved
278 - 27F	External Printer Port
2F0 - 2FF	Reserved
300 - 31F	External Prototyping Card
320 - 32F	External Hard Disk Controller
380 - 38F	External SDLC Serial RS232C Port
3A0 - 3AF	Reserved
3B0 - 3BB	External Monochrome VDU Controller
3BC - 3BF	Printer Port
3C0 - 3CF	External Graphics Controller
3D0 - 3DF	External Colour/Graphics Controller

I/O address above 03FFh, if accessed, wrap around and are mapped onto the range 0000h-03FFh.

External cluster controllers at 0790h-0793h, 0B90h-0B93h, 1390h-1393h and 2390h-2393h wrap around to I/O addresses 0390h-0393h respectively.

1.5 Direct Memory Access (DMA)

The Amstrad PPC supports four DMA channels on the system board, using an 8237-4 DMA controller and programmable page registers to extend its addressing range from 64k bytes to the full 1M byte processor address range. Each channel is able to transfer data in blocks of up to a maximum of 64K bytes within a page. The DMA channels are for 8-bit data transfers between (8-bit) I/O devices and 8-bit or 16-bit memory.

In peripheral (slave) mode, CPU I/O address lines A0 - A3 are connected conventionally so that 16 command codes appear in the order described in the 8237 data sheets (See section 3.5).

The DMA controller CLK is driven at 4MHz (+/- 0.1%). In master mode during DMA transfers on channels 1,2 and 3, one wait state is added resulting in a five-clock DMA bus cycle of 1.25μS. Channel 0 transfers have a four-clock bus cycle of 1μS.

The DMA channel request signals are as follows:

DMA Channel	USE
0	8253 Timer/Counter OUT1 output - for memory refresh.
1	Spare for use by expansion bus. Used by external SDLC Serial Port.
2	765 Floppy Disk Controller DRQ output. Available on the expansion bus.
3	Spare for use by expansion bus. Used by external Hard Disk Controller.

1.5.1 DMA Page Registers

DMA channels 1, 2 and 3 can address the entire 1M byte addressing range of the CPU through the use of their associated DMA page registers. There are three DMA registers, one each for channels 1 through 3. Each page register defines for its channel which one of sixteen 64K byte pages in the 1M byte address range DMA transfers are to occur. The page registers are static so that modulo 64K byte addressing occurs at page boundaries.

The DMA page register bit assignments are as follows:

Bit	Output Use
7-4	Not Connected
3	Address bit A19
2	Address bit A18
1	Address bit A17
0	Address bit A16

1.5.2 DMA Initialisation

Following a reset, system (ROS) initialisation firmware (in the ROS) sets up the 8237 DMA controller for channel 0 (dynamic refresh) operation as follows:

Function	Initialised State
Word Count	64K Transfers
Mode Register	Read Autoinitialise Increment Single Mode
Command Register	Disable Memory to Memory Enable Controller Normal Timing Fixed Priority Late Write DREQ Active High DACK Active Low
Mask Register	Clear Channel 0 Mask Bit

After power-up or system reset the DMA page registers are undefined and are initialised to zero by the ROS firmware and all 8237 internal locations for channels 1-3 are initialised to a state comparable to the channel zero initialisation above.

Following industry compatibility, memory to memory DMA is not supported on the PPC. It is prohibited due to timing considerations.

1.6 System Interrupts

Nine levels of hardware interrupt are provided for in the system by the CPU Non Maskable Interrupt (NMI) and by an 8259A-2 Interrupt Controller. All levels including NMI, are maskable under software control.

CPU I/O address line A0 is connected conventionally so that the command codes appear in the order described in the 8259 data sheets. The SP/EN pin is tied high signifying that the device is to be hardware un-buffered and designated as a master, not a slave.

1.6.1 Interrupt Levels

The interrupt levels are assigned as follows:

Level	Assigned Function
NMI	Memory Parity Error and 8087 NDP INT output.
0	8253 Timer/Counter Out0 output.
1	Keyboard Scan Code Receiver.
2	146818 Real Time Clock IRQ output. Available on the expansion bus. May be used by Enhanced Graphics Adapter
3	Used by Modem Serial Port (COM2) and external SDLC Serial Port. Available on the expansion bus.
4	Primary Serial port (COM1). Available on the expansion bus. Used by external SDLC Serial Port.
5	Hard Disk Controller. Available on the expansion bus.
6	765 Floppy Disk Controller INT output. Available on the expansion bus.
7	Parallel Printer Port. Available on the expansion bus. Used by external Printer Port (secondary) and Printer Port (ternary) on external Monochrome VDU Controller.

1.6.2 Interrupt Controller Initialisation

Following a reset, the initialisation firmware in the ROS sets the 8259 Interrupt Controller to operate as follows:

8086 system, Single (not cascaded),
Normal fully nested (not special),
Edge-triggered,
Buffered mode - slave,
Normal EOI (not auto),
Fixed priority - level 0 highest, level 7 lowest.

The system (ROS) firmware initialises the 8259 address bits such that IRQ0 through IRQ7 appear in the CPU interrupt vector space at interrupts 8 through 15 respectrively. NMI is configured to CPU interrupt vector 2.

1.6.3 NMI Mask Control

The NMI Mask Control is a write only register at I/O address 0A0h and allows the CPU non-maskable interrupt (NMI) input to be enabled or disabled by software. The Bit assignments are as follows:

Bit	Output Use
7	Enable NMI.
6 - 0	Not Connected

Following a reset NMI is disabled.

NMI can be connected to the 8087 NDP, the on-board memory parity check circuit, and the expansion bus I/OCHCK (I/O Channel Check).

1.7 Programmable Interval Timers

Three programmable timer/counters are provided at I/O Addresses 040 - 043 by an 8253 Programmable Interval Timer (PIT) device. They are defined as follows:

Counter	Use
0	General Purpose Timer.
1	Used by DMA channel 0 (for dynamic ram refresh).
2	Tone Generation for Speaker.

1.7.1 Timer Configuration

The 8253 timers are configured as follows:

Function	Configuration
CLK 0,1,2	1.193 MHz +/- 0.1% (54.925493 ms per count)
GATE 0,1	Always 'ON'.
GATE 2	Controlled via Port B (System Control Channel) Speaker Modulate output.
OUT 0	Interrupts on 8259 PIC IR0 input.
OUT 1	Requests on 8237 DMA DREQ0 input.
OUT 2	Logical 'AND' with Port B (System Control Channel) Speaker Drive output. Also goes to Port C (System Status-2 Channel) as an input.

1.7.2 Counter 1 initialisation

Following a reset, the system initialisation firmware in the ROS programs the 8253 PIT for counter 1 (dynamic ram refresh) operation as a rate generator producing a signal with a period of 15.13 μS. There are no restrictions requiring the initialisation and programming of counters 0 and 2.

1.8 System Status and Control

Two system status input channels and four output channels are provided on-board. Ports A, B and C emulate a pre-programmed