INTERFACE SLOTS

GENERAL

The Organiser interfaces to the outside world through three slots:

1. SLOT 1. Side entry, top (nearest display)
2. SLOT 2. Side entry, bottom
3. SLOT 3. Top entry

Slots 1 and 2 are generally used for memory devices such as datapacks and rampacks, and slot 3 is normally used for communications or other interfaces. Electrically all three slots are very similar, and the distinction is for ergonomic reasons. Internally the three slots are connected together as a bus, carrying 8 bit bi-directional data, power and control lines to select and control devices plugged in.

This section describes the bus hardware in general terms, and should be read together with the sections on specific devices and control software to gain a full understanding of its operation.

SLOT CONTROL BUS

All three slots have 16 connections. In general they are connected as a bus, but there are some minor differences in signals particularly to slot 3. The slot signals and their functions are listed below:

see Datapack Connector for pinout.

POWER RAILS

A detailed description of the power supply circuitry is included in chapter Power Supply Board. The main properties of the externally available power rails are included here for reference.

Vb (slot 3 only)

This is the main Organiser system power rail, and is fed by the Organiser battery via a forward diode. All Organiser regulated power rails are derived from this rail. Vb can be used as a power output or as an external power input. As a power output, the battery voltage minus a diode drop will appear at this pin (5.5 to 8.5 volts dependent on battery condition). As a power input, the voltage applied should be higher than the battery voltage to ensure no current drain from the battery. It is recommended that an external power source also feeds the Vb pin through a forward diode, to ensure no reverse current to the external source when it is powered off. In this configuration power for the system is drawn from either the internal battery or the external power source, whichever is supplying the higher voltage. Vb should be between 5.5 and 11.0 volts under a maximum system load of 175 mA. The lower limit is determined by the dropout voltage of the 5 volt pass regulators (the low battery indicator is triggered at approx. 5.3 volts on Vb). The upper limit is defined primarily by the Vcc3 pass regulator - see below.

Vcc3 (all slots)

This is the main power rail to the slots, and is regulated to 5 volts +/-5%. It is derived from the Vb rail above. The regulator is a low-dropout type with a PNP pass transistor rated at 1 watt. At a Vb voltage of 11 volts the maximum DC current capacity of Vcc3 is therefore 167 ma (167*(11-5)=1000 mW). In practice 150 ma should be used as the rating of this rail, remembering that all three slots are powered in parallel. The power budget allocated to each slot is 40 ma for an idle device and 70 ma for an active selected device. Only one slot should be active at any one time, giving 40+40+70=150 ma as the peak power drain with three devices present and one active.
Vcc3 is switched on and off by the PACON_B signal from the processor port 6, bit 7. When this bit is defined as input the PACON_B signal is pulled high to leave the regulator in the off state. (When off, only leakage current of a few nA will be supplied to the Vcc3 rail). To switch Vcc3 on, port 6 bit 7 should be defined as output and low (0).

Vpp (slots 1,2)

This rail is designed specifically for programming of datapack ')"; onMouseout="hideddrivetip()"> EPROM s, and may assume one of three voltages:

1. 0 volts when Vcc3 is off
2. 4.5 volts when Vcc3 is on (diode drop below Vcc3)
3. 21 volts +/-2% when the 21 volt regulator is on

The 21 volt state is normally used in a pulsed mode under software control, for programming ')"; onMouseout="hideddrivetip()"> EPROM s with defined algorithms. This is discussed further in the Datapack section of the manual.

DATA BUS (PROCESSOR PORT 2)

The data bus SD0-SD7 is an 8 bit bi-directional bus to all three slots, and is controlled from the processor I/O port 2. The notes below summarise port 2 operation in the context of the Organiser system.

The primary use of port 2 is as an eight bit parallel I/O port. Two registers control this function:

• Port 2 data register $0003
• Port 2 DDR $0001

The DDR determines the I/O direction of the port bits (0 for input, 1 for output). Only 2 bits of the DDR are active:

• Bit 0 defines the direction of SD0
• Bit 1 defines the direction of SD1-SD7

The DDR is a write-only register, and read-modify-write instructions should be used with caution.

With the DDR set to input, data present on the bus can be read through the data register. If no slot is active a $00 will be returned, defined by the eight pull-down resistors on the data lines.

When the Organiser is off (processor in standby mode) the DDR is automatically set to input, and remains in this state on system initialisation. In subsequent operation this should be used as the rest state, and in particular should always be set to input whenever Vcc3 is switched off.

With the DDR set to output, data can be set onto the bus by a write to the data register. Data is latched into the register, and will remain on the bus until a further write. Note that data can be written to the data register with the DDR set to input, and this data will be set onto the bus when the DDR is turned round.

Control of the bus and bus direction is entirely under software control. Control of devices in the slots is described further in the next section, but it is important to stress here that control of the port 2 DDR is vital for proper bus operation. A condition where the DDR is set to output and a slot device is also outputting to the bus should not be allowed to occur if bus contention and possible device damage are to be avoided.

In addition to the data bit I/O function, each bit of port 2 has a secondary function which may be selected under software control. When selected, the relevant bits assume their secondary function, overriding the DDR setting where necessary. The secondary functions are described in the processor manual. An example of their use is the Organiser RS232 interface, which uses the internal serial communications interface and the port 2 Tx and Rx bits. Note that in special cases such as this, various bits of the data bus may separately be defined as inputs and outputs simultaneously.

CONTROL LINES (PROCESSOR PORT 6)

Port 6 of the processor is an 8 bit I/O port controlled by two registers:

• Port 6 data register $0017
• Port 6 DDR $0016

The DDR determines the direction of the port bits (0 for input, 1 for output). Each bit of the DDR determines the direction of the corresponding bit of the data register. The DDR is a write only register, and read-modify-write instructions should be used with caution.

When the Organiser is off (processor in standby mode), the DDR is automatically set to input and remains in this state on system initialisation. In this case the lines from the ports will take up states defined by the relevant external pull-up and pull-down resistors.

The port bits are defined as follows: