DS Memory Information

ARM7

Name Region base End Size Mirrored Width / modes
BIOS (ARM7) 0x00000000 0x00003FFF 16 KB no unknown
Main RAM 0x02000000 0x023FFFFF 4 MB (8 MB) yes 16 / all
Shared RAM 0x037F8000 0x037FFFFF 32 KB ? 32 / 16,32
Private RAM 0x03800000 0x0380FFFF 64 KB yes 32 / 16,32
Registers 0x04000000 * * * *
Wifi Control 0x04800000 0x04800FFF * yes** 16
Wifi MAC memory 0x04804000 0x04805FFF 8 KB yes** 16
GBA cart ROM 0x08000000 0x09FFFFFF 32 MB no 16 / all
GBA cart RAM 0x0A000000 0x0A00FFFF 64 KB yes 8 / 8

The ARM7 BIOS is protected via a PC check. The portion below PROTECTION_CR? can be read when PC < PROTECTION_CR?, and the portion beyond it can be read when PC < 0x4000.

ARM9

Name Region base Size Mirrored Width / modes
ITCM 0x00000000* 16 KB no 32 / all
DTCM 0x00800000* 16 KB no 32 / all
Main RAM 0x02000000 4 MB (8 MB) yes 16 / all
Shared RAM 0x03000000 32 KB yes 32 / 16,32
Registers 0x04000000 * * *
Palette RAM 0x05000000 2 KB yes 16 / 16,32
Video RAM 0x06000000 ? ? 16 / 16,32
Sprite RAM 0x07000000 2 KB yes 16 / 16,32
GBA cart ROM 0x08000000 32 MB no 16 / all
GBA cart RAM 0x0A000000 64 KB yes 8 / 8
BIOS (ARM9) 0xFFFF0000 4 KB no unknown / all

The Main RAM is always available to both processors, although one has priority over it, and the other will be delayed if both try to access it at the same time.

The 'shared' RAM actually consists of two banks of 16 KB each, and either one only available to a single processor at a time. They can be switched back and forth, to implement a buffer passing scheme for e.g. wireless packets or a sound buffer.

ITCM and DTCM can be relocated using the system control coprocessor CP15

The ARM9 BIOS provides a handful of functions, but does little in the way of system setup. It clears some memory, then waits for the ARM7 bios to signal that system init is complete.

 

 

Registers

Name Address:Width Description
DISPLAY_CR 0x04000000:32
WAIT_CR 0x04000204:16 Wait state control register
KEYS 0x04000130:16 Keys register
IME 0x04000208:32 Interrupt master enable
IE 0x04000210:32 Interrupt enable
IF 0x04000214:32 Interrupt flags
CARD_CR1 0x040001A0:32 Card CR1
CARD_CR2 0x040001A4:32 Card CR2
CARD_PARAMS 0x040001A8:64 Card command
CARD_DATA 0x04100000:32 Card data
CARD_DATA_RD 0x04100010:32 Card data
HALT_CR 0x04000300:16 Halt control register
POWER_CR 0x04000308:16 Power control register
PROTECTION_CR 0x04000308:32 Protection control register (ARM7)
SOUND504 0x04000504:16 Sound bias register (ARM7)
a1 b1 c1 d1
a2 b2 c2 d2

 

DMA stands for Direct Memory Access, referring to the ability of peripherial hardware to directly access memory, independant of the CPU.

DMA registers

Address Name
0x040000B0:32 R/W DMA0_SRC (0ffffffe)
0x040000B4:32 R/W DMA0_DST (0ffffffe)
0x040000B8:32 R/W DMA0_CR (ffffffff)
0x040000BC:32 R/W DMA1_SRC (0ffffffe)
0x040000C0:32 R/W DMA1_DST (0ffffffe)
0x040000C4:32 R/W DMA1_CR (ffffffff)
0x040000C8:32 R/W DMA2_SRC (0ffffffe)
0x040000CC:32 R/W DMA2_DST (0ffffffe)
0x040000D0:32 R/W DMA2_CR (ffffffff)
0x040000D4:32 R/W DMA3_SRC (0ffffffe)
0x040000D8:32 R/W DMA3_DST (0ffffffe)
0x040000DC:32 R/W DMA3_CR (ffffffff)

Format of the control registers:

Enable:

  • W0: Stop DMA
  • W1: Activate DMA
  • R1: Busy
  • R0: Ready

Size:

  • 0: Halfword (16 bits)
  • 1: Word (32 bits)

Timing mode:

  • 0: Immediately
  • 1: Wait until V-Blank
  • 2: Wait until H-Blank
  • 3: Display synchronize
  • 4: ?
  • 5: Card
  • 6: ?
  • 7: ?

Source mode:

  • 0: Increment
  • 1: Decrement
  • 2: Fixed
  • 3: Undefined

Destination mode:

  • 0: Increment
  • 1: Decrement
  • 2: Fixed
  • 3: Increment, but reload on completion

FIFO

ARM9 view: MAGIC180 (0x04000180:16)

Bits Mode Description
15 ? ?
14 R/W ?
13..12 ? ?
11..8 R/W ARM7.MAGIC180.data
7..4 ? ?
3..0 W data

ARM7 view: MAGIC180 (0x04000180:16)

Bits Mode Description
15..12 ? ?
11..8 W data
7..4 ? ?
3..0 R ARM9.MAGIC180.data